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實验三_用状态机实现序列检测器的设计1.doc 9页
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實验三_用状态机实现序列检测器的设计1
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西南科技大学
实 验 报 告
FPGA现代数字系统设计
实验题目：用状态机实现序列检测器的设计
专业班级：
对抗0802班
学生姓名：
学生学号：
实验时间：
指导教师：
用状态机实现序列检测器的设计
一、实验目的：
用状态机实现序列检测器的设计，并对其进行仿真和硬件测试。
二、原理说明：
序列检测器可用于检测一组或多组由二进制码组成的脉冲序列信号，当序列检测器连续收到一组串行二进制码后，如果这组码与检测器中预先设置的码相同，则输出a，否则输出b。由于这种检测的关键在于正确码的收到必须是连续的，这就要求检测器必须记住前一次的正确码及正确序列，直到在连续的检测中所收到的每一位码都与预置数的对应码相同。在检测过程中，任何一位不相等都将回到初始状态重新开始检测。例3-1描述的电路完成对序列数&&的。当这一串序列数高位在前（左移）串行进入检测器后，若此数与预置的密码数相同，则输出“a”，否则仍然输出“b”。
三、实验内容：
1. 编写由两个主控进程构成的有限状态机。画出状态图，并给出其仿真测试波形；
第一个主控进程schk程序：
module schk(DIN,CLK,CLR,AB);
input DIN,CLK,CLR;
output[3:0]
reg [7:0] Q;
reg [3:0] AB;
idle = 8'b,
parameter data=8’b;
always @(posedge CLK or negedge CLR)
if(DIN==data[7]) Q&=a;
if(DIN== data[6]) Q&=b;
if(DIN== data[5]) Q&=c;
if(DIN== data[4]) Q&=d;
if(DIN== data[3]) Q&=e;
if(DIN== data[2]) Q&=f;
if(DIN== data[1]) Q&=g;
if(DIN== data[0]) Q&=h;
always @(Q)
if(Q==h) AB &= 4'b1010 ;
else AB &= 4'b1011 ;
功能仿真：
时间仿真：
第一个主控进程xulie程序:
module xulie(clk, din8, reset, din);
input[7:0] din8;
s0 = 3'b000
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